Thin film transistor (TFT) is a kind of a field effect transistor (FET). In typical FET, the source and drain and the channel region are formed in the substrate composed of single crystal silicon. The channel region of the TFT is different from the conventional FET. Namely, the channel region of the TFT is formed in a polysilicon or amorphous silicon layer on a substrate. For the application, the TFT can region of the TFT is formed in a polysilicon or amorphous silicon layer on a substrate. For the application, the TFT can be used in flat panel display as switching transistors and in static random access memory as load devices. By varying the transverse electrical field, it is possible to control the current flow by modulating the conductance of the channel. If the drain bias is applied such that source and drain remain reverse-bias. A positive bias is applied to the gate of the NMOS, electrons will be attracted to the channel region, once enough electrons are drawn into the channel region by the positive gate voltage, and the channel connects the source and the drain.
One of the key parameters to determine the performance of the device is the drain off-set structure. The off-set structure is parts outside the gate electrode. The function of the off-set structure is similar to the lightly doped drain (LDD) structure in FET. The drain off-set structure can reduce the short channel effect or reduce punch-through effect caused by hot carrier and the structure also reduces the off-state leakage. Apparently, one way to form a quality SRAM is to decrease the on off-current and increase the on-current.
FIG. 11 shows a cross sectional view of a conventional polysilicon PMOS cell. In the cell, isolation structures composed of oxide 4a are formed in the substrate 2a for isolation. A driver NMOS is formed on the top of the substrate 2a. A transistor 8a is located adjacent to the NMOS. A gate 10a isolated by dielectric material 6a is formed on the driver NMOS, and a polysilicon layer 10a is used to connect the driver NMOS and the doped region of the transistor 8a. The gate 10a and the polysilicon layer 10a are composed of N type polysilicon. A P conductive type polysilicon layer 12a goes over the dielectric layer 6a. A part of the layer 12a is implanted to define the source and drain. An off-set can be found adjacent to the drain. The separation between the source and drain defines the channel. The channel is oriented in a direction substantially parallel to the substrate, this leads to the conventional structure occupies a large cell area. It is not suitable to the trend of manufacture with high packing density. The channel formed of polysilicon provides smaller on-current compared to monocrystalline silicon channel.
One of the approaches for the off- set structure is disclosed in U.S. Pat. No. 5,001,540 to Ishihara, he develops a dual gate TFT with off-set structure. The off-set region is the extension of a layer used to form the channel region. The dopant concentration is the same with that of channel region. Further, in the structure, the dimension of the off-set is determined by the width of the side walls spacers. Shepard provides a vertical dual gate thin film transistor, the article can be seen in U.S. Pat. No. 5,574,294. Shepard disclosed a self-aligned process for forming the source and drain regions in a dual gate TFT and further allows for the formation of off-set. Recently, some researches and developments have been approached to develop a vertical thin film transistor. The channel of the device is vertical to the surface of the substrate. Some arts provide a device cell with source, channel and drain that are vertically formed in a trench. The devices provide an advantage of higher density than others.